`timescale 1ns / 1ps

module tick(
    input clk,
    output msc
);
    reg [19:0] cnt;
    reg msc_reg;
    always @ (posedge clk)
    begin
        if(cnt==20'h7A11F)//0x7A11F = 499999
            begin
                msc_reg <= ~msc_reg;
                cnt <= 20'h0;
            end 
        else begin
           cnt <= cnt + 1;
        end
    end
    assign msc = msc_reg;
endmodule

module flash_rate(
    input clk,
    input [3:0]ms1,
    input [3:0]ms2,
    input [3:0]s1,
    input [3:0]s2,
    input [3:0]m1,
    input [3:0]m2,
    output [23:0] bit_out
    );

    reg [17:0] cnt;

    reg [1:0] fr;
    //fr decide which bit to light on
    //00 - 1 & 5
    //01 - 2 & 6
    //10 - 3 & 7
    //11 - 4 & 8
    always @ (posedge clk)
    begin
        if(cnt==18'h3ffff)
            begin
                if(fr == 2'd3) fr <= 2'b0;
                else fr <= fr+1; 
                cnt <= 20'h0;
            end 
        else begin
           cnt <= cnt + 1;
        end
    end
    
    //control gnd ports to make it scan.
    bits_8 u0(.f(fr),.bit1(m1),.bit2(m2),.bit4(s1),.bit5(s2),.bit7(ms1),.bit8(ms2),.bit_out(bit_out));
    
endmodule